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integrated device technology, inc. commercial temperature range october 1996 ?1996 integrated device technology, inc. dsc-2943/3 idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram features: ? true dual-ported memory cells which allow simulta- neous access of the same memory location ? high-speed access commercial: 25/35/55ns (max.) ? low-power operation idt70v07s active: 450mw (typ.) standby: 5mw (typ.) idt70v07l active: 450mw (typ.) standby: 5mw (typ.) ? idt70v07 easily expands data bus width to 16 bits or more using the master/slave select when cascading more than one device ?m/ s = h for busy output flag on master m/ s = l for busy input on slave ? busy and interrupt flags ? on-chip port arbitration logic ? full on-chip hardware support of semaphore signaling between ports ? fully asynchronous operation from either port ? devices are capable of withstanding greater than 2001v electrostatic discharge ? lvttl-compatible, single 3.3v ( 0.3v) power supply ? available in 68-pin pga, 68-pin plcc, and a 64-pin tqfp description: the idt70v07 is a high-speed 32k x 8 dual-port static ram. the idt70v07 is designed to be used as a stand-alone dual-port ram or as a combination master/slave dual- port ram for 16-bit-or-more word systems. using the idt master/slave dual-port ram approach in 16-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. functional block diagram notes: 1. (master): busy is output; (slave): busy is input. 2. busy and int outputs are non-tri-stated push-pull. 1 i/o control address decoder memory array arbitration interrupt semaphore logic address decoder i/o control r/ w l ce l oe l busy l a 14l a 0l 2943 drw 01 i/o 0l - i/o 7l ce l oe l r/ w l sem l int l m/ s busy r i/o 0r -i/o 7r a 14r a 0r sem r int r ce r oe r (2) (1,2) (1,2) (2) r/ w r ce r oe r r/ w r 15 15 6.37 for latest information contact idts web site at www.idt.com or fax-on-demand at 408-492-8391.
6.37 2 idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range this device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by ce permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idts cmos high-performance technol- ogy, these devices typically operate on only 450mw of power. the idt70v07 is packaged in a ceramic 68-pin pga, a 68- pin plcc, and a 80-pin thin plastic quad flatpack (tqfp). pin configurations (1,2) 2943 drw 02 12 13 14 15 16 17 18 index 19 20 21 22 98765432168676665 27 28 29 30 31 32 33 34 35 36 37 38 39 v cc v cc i/o 1r i/o 2r i/o 3r i/o 4r int l gnd a 4l a 3l a 2l a 1l a 0l a 3r a 0r a 1r a 2r i/o 2l a 5l 11 10 m/ s 23 24 25 26 40 41 42 43 58 57 56 55 54 53 52 51 50 49 48 59 60 47 46 45 44 64 63 62 61 i/o 3l gnd i/o 0r v cc a 4r busy l gnd busy r int r a 12r i/o 7r n/c gnd oe r r/ w r sem r ce r ce l n/c i/o 0l i/o 1l idt70v07 j68-1 plcc top view (3) i/o 4l i/o 5l i/o 6l i/o 7l i/o 5r i/o 6r a 12l a 11r a 10r a 9r a 8r a 7r a 6r a 5r a 11l a 10l a 9l a 8l a 7l a 6l a 13r a 13l a 14l a 14r r/ w l oe l sem l index i/o 2l v cc gnd gnd a 4r busy l busy r gnd m/ s oe l i/o 1l r/ w l ce l sem l v cc oe r ce r r/ w r sem r a 12r gnd i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l i/o 0r i/o 1r i/o 2r v cc i/o 3r i/o 4r i/o 5r i/o 7r a 11r a 10r a 9r a 8r a 7r a 6r a 5r a 3r a 2r a 1r a 0r a 0l a 1l a 2l a 3l a 4l a 6l a 7l a 8l a 9l a 10l a 11l a 12l i/o 0l 2943 drw 03 a 13r a 13l 70v07 pn80-1 tqfp top view (3) 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 46 45 44 43 42 41 56 55 54 53 52 51 50 47 48 49 32 31 30 29 28 27 26 25 24 23 22 21 63 62 61 64 33 34 35 36 37 38 39 40 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 n/c n/c a 14l n/c n/c n/c n/c a 14r n/c n/c 17 18 19 20 57 58 59 60 a 5l n/c int l int r n/c n/c n/c i/o 6r n/c n/c notes: 1. all vcc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. 3. this text does not indicate the actual part marking.
idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range 6.37 3 notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground supply. 3. this text does not indicate orientation of the actual part-marking. 2943 tbl 01 left port right port names ce l ce r chip enable r/ w l r/ w r read/write enable oe l oe r output enable a 0l C a 14l a 0r C a 14r address i/o 0l C i/o 7l i/o 0r C i/o 7r data input/output sem l sem r semaphore enable int l int r interrupt flag busy l busy r busy flag m/ s master or slave select v cc power gnd ground pin names 2943 drw 04 51 50 48 46 44 42 40 38 36 53 55 57 59 61 63 65 67 68 66 13579 11 13 15 20 22 24 26 28 30 32 35 idt70v07 g68-1 68-pin pga top view abcdefgh j k l 47 45 43 41 34 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 19 17 56 58 60 62 64 11 10 09 08 07 06 05 04 03 02 01 52 54 49 39 37 a 5l int l sem l ce l v cc oe l r/ w l i/o 0l n/c gnd gnd i/o 0r v cc n/c oe r r/ w r sem r ce r gnd busy r busy l m/ s int r gnd a 1r index a 4l a 2l a 0l a 3r a 2r a 4r a 5r a 7r a 6r a 9r a 8r a 11r a 10r a 12r a 0r a 7l a 6l a 3l a 1l a 9l a 8l a 11l a 10l a 12l v cc i/o 2r i/o 3r i/o 5r i/o 6r i/o 1r i/o 4r i/o 7r i/o 1l i/o 2l i/o 4l i/o 7l i/o 3l i/o 5l i/o 6l a 13r a 13l a 14r a 14l (3) pin configurations (cont'd) (1,2)
6.37 4 idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range truth table i C non-contention read/write control inputs (1) outputs ce ce ce ce ce r/ w w w w w oe oe oe oe oe sem sem sem sem sem i/o 0-7 mode h x x h high-z deselected: power-down l l x h data in write to memory l h l h data out read memory x x h x high-z outputs disabled note: 2943 tbl 02 1. a 0l a 14l 1 a 0r a 14r. truth table ii C semaphore read/write control (1) inputs outputs ce ce ce ce ce r/ w w w w w oe oe oe oe oe sem sem sem sem sem i/o 0-7 mode h h l l data out read data in semaphore flag h x l data in write i/o 0 into semaphore flag l x x l not allowed note: 2943 tbl 03 1. there are eight semaphore flags written to via i/o 0 and read from all i/o's (i/o 0 -i/o 7 ). these eight semaphores are addressed by a 0 - a 2 . recommended operating temperature and supply voltage ambient grade temperature gnd v cc commercial 0 c to +70 c 0v 3.3v 0.3v 2943 tbl 05 absolute maximum ratings (1) symbol rating commercial unit v term (2) terminal voltage C0.5 to +4.6 v with respect to gnd t a operating 0 to +70 c temperature t bias temperature C55 to +125 c under bias t stg storage C55 to +125 c temperature i out dc output 50 ma current notes: 2943 tbl 04 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 0.3v for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > vcc + 0.3v. capacitance (1) (t a = +25 c, f = 1.0mhz)tqfp only symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 9 pf c out output v out = 3dv 10 pf capacitance notes: 2943 tbl 07 1. this parameter is determined by device characterization but is not production tested. 2. 3dv represents the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. recommended dc operating conditions (2) symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v gnd supply voltage 0 0 0 v v ih input high voltage 2.0 v cc +0.3 v v il input low voltage C0.3 (1) 0.8 v notes: 2943 tbl 06 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 0.3v.
idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range 6.37 5 dc electrical characteristics over the operating temperature and supply voltage range (v cc = 3.3v 0.3v) idt70v07s idt70v07l symbol parameter test conditions min. max. min. max. unit |i li | input leakage current (1) v cc = 3.6v, v in = 0v to v cc 105 m a |i lo | output leakage current ce = v ih , v out = 0v to v cc 105 m a v ol output low voltage i ol = 4ma 0.4 0.4 v v oh output high voltage i oh = -4ma 2.4 2.4 v 2943 tbl 08 dc electrical characteristics over the operating temperature and supply voltage range (1) (v cc = 3.3v 0.3v) 70v07x25 70v07x35 70v07x55 test symbol parameter condition version typ. (2) max. typ. (2) max. typ. (2) max. unit i cc dynamic operating ce = v il , outputs open coml. s 100 170 90 140 90 140 ma current sem = v ih l 100 140 90 120 90 120 (both ports active) f = f max (3) i sb1 standby current ce r = ce l = v ih coml. s 14 30 12 30 12 30 ma (both ports ttl sem r = sem l = v ih l12 24 10 24 10 24 level inputs) f = f max (3) i sb2 standby current ce "a" = v il and ce "b" = v ih (5) coml. s 50 95 45 87 45 87 ma (one port ttl active port outputs open, l 50 85 45 75 45 75 level inputs) f = f max (3) sem r = sem l = v ih i sb3 full standby current both ports ce l and coml. s 1.0 6 1.0 6 1.0 6 ma (both ports all ce r > v cc - 0.2v l 0.2 3 0.2 3 0.2 3 cmos level inputs) v in > v cc - 0.2v or v in < 0.2v, f = 0 (4) sem r = sem l > v cc - 0.2v i sb4 full standby current ce "a" < 0.2v and coml. s 60 90 55 85 55 85 ma (one port all ce "b" > v cc - 0.2v (5) l60 80 55 74 55 74 cmos level inputs) sem r = sem l > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v active port outputs open f = f max (3) notes: 2943 tbl 09 1. "x" in part numbers indicates power rating (s or l). 2. v cc = 3.3v, t a = +25 c, and are not production tested. i ccdc = 80ma (typ.) 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1 / t rc, and using ac test conditions of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. 5. port "a" may be either left or right port. port "b" is the opposite from port "a". note: 1. at vcc 2.0v input leakages are undefined.
6.37 6 idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range ac test conditions input pulse levels gnd to 3.0v input rise/fall times 5ns max. input timing reference levels 1.5v output reference levels 1.5v output load figures 1 and 2 2943 tbl 10 figure 1. ac output test load figure 2. output test load (for t lz , t hz , t wz , t ow ) * including scope and jig. 2943 drw 06 590 w 30pf 435 w 3.3v data out busy int 590 w 5pf 435 w 3.3v data out 2943 drw 05 ce 2943 drw 07 t pu i cc i sb t pd 50% 50% timing of power-up power-down notes: 2943 tbl 11 1. transition is measured 200mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . 4. "x" in part numbers indicates power rating (s or l). ac electrical characteristics over the operating temperature and supply voltage range (4) idt70v07x25 idt70v07x35 idt70v07x55 symbol parameter min. max. min. max. min. max. unit read cycle t rc read cycle time 25 35 55 ns t aa address access time 25 35 55 ns t ace chip enable access time (3) 2535 55ns t aoe output enable access time 15 20 30 ns t oh output hold from address change 3 3 3 ns t lz output low-z time (1, 2) 33 3ns t hz output high-z time (1, 2) 1520 25ns t pu chip enable to power up time (2) 00 0ns t pd chip disable to power down time (2) 2535 50ns t sop semaphore flag update pulse ( oe or sem )151515ns t saa semaphore address access time 35 45 65 ns
idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range 6.37 7 waveform of read cycles (5) notes: 1. timing depends on which signal is asserted last, oe or ce . 2. timing depends on which signal is de-asserted first, ce or oe . 3. t bdd delay is required only in cases where the opposite port is completing a write operation to the same address location. for simultaneous read operations busy has no relation to valid output data. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa or t bdd . 5. sem = v ih . notes: 2943 tbl 12 1. transition is measured 200mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . either condition must be valid for the entire t ew time. 4. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 5. "x" in part numbers indicates power rating (s or l). ac electrical characteristics over the operating temperature and supply voltage (5) idt70v07x25 idt70v07x35 idt70v07x55 symbol parameter min. max. min. max. min. max. unit write cycle t wc write cycle time 25 35 55 ns t ew chip enable to end-of-write (3) 20 30 45 ns t aw address valid to end-of-write 20 30 45 ns t as address set-up time (3) 000ns t wp write pulse width 20 25 40 ns t wr write recovery time 0 0 0 ns t dw data valid to end-of-write 15 20 30 ns t hz output high-z time (1, 2) 15 20 25ns t dh data hold time (4) 000ns t wz write enable to output in high-z (1, 2) 15 20 25ns t ow output active from end-of-write (1, 2, 4) 000ns t swrd sem flag write to read time 5 5 5 ns t sps sem flag contention window 5 5 5 ns t rc r/ w ce addr t aa oe 2943 drw 08 (4) t ace (4) t aoe (4) (1) t lz t oh (2) t hz (3, 4) t bdd data out busy out valid data (4)
6.37 8 idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range timing waveform of write cycle no. 1, r/ w w w w w controlled timing (1,5,8) timing waveform of write cycle no. 2, ce ce ce ce ce controlled timing (1,5) r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in ce or sem (6) (4) (4) (3) 2943 drw 09 (7) (7) (9) 2943 drw 10 t wc t as t wr t dw t dh address data in r/ w t aw t ew (3) (2) (6) ce or sem (9) notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a low ce and a low r/ w for memory array writing cycle. 3. t wr is measured from the earlier of ce or r/ w (or sem or r/ w ) going high to the end of write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce or r/ w . 7. this parameter is guaranteed by device characterization, but is not production tested. transition is measured + 200mv from steady state with the output test load (figure 2). 8. if oe is low during r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . t ew must be met for either condition.
idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range 6.37 9 timing waveform of semaphore read after write timing, either side (1) notes: 1. d or = d ol = v il , ce r = ce l = v ih . 2. all timing is the same for left and right ports. port "a" may be either left or right port. "b" is the opposite from port "a". 3. this parameter is measured from r/ w "a" or sem "a" going high to r/ w b or sem "b" going high. 4. if t sps is not satisfied, there is no guarantee which side will be granted the semaphore flag. sem "a" 2943 drw 12 t sps match r/ w "a" match a 0"a" -a 2"a" side ? (2) sem "b" r/ w "b" a 0"b" -a 2"b" side (2) ? notes: 1. ce = v ih for the duration of the above timing (both write and read cycle). 2. "data out valid" represents all i/o's (i/o 0 -i/o 7 ) equal to the semaphore value. timing waveform of semaphore write contention (1,3,4) sem 2943 drw 11 t aw t ew t sop i/o 0 valid address t saa r/ w t wr t oh t ace valid address data in valid data out t dw t wp t dh t as t swrd t aoe read cycle write cycle a 0 -a 2 oe valid (2)
6.37 10 idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range ac electrical characteristics over the operating temperature and supply voltage range (6) idt70v07x25 idt70v07x35 idt70v07x55 symbol parameter min. max. min. max. min. max. unit busy timing (m/ s s s s s = v ih ) t baa busy access time from address match 25 35 45 ns t bda busy disable time from address not matched 25 35 45 ns t bac busy access time from chip enable low 25 35 45 ns t bdc busy disable time from chip enable high 25 35 45 ns t aps arbitration priority set-up time (2) 5 5 5 ns t bdd busy disable to valid data (3) 35 40 50ns t wh write hold after busy (5) 20 25 25 ns busy timing (m/ s s s s s = v il ) t wb busy input to write (4) 0 0 0 ns t wh write hold after busy (5) 20 25 25 ns port-to-port delay timing t wdd write pulse to data delay (1) 55 65 85ns t ddd write data valid to read data delay (1) 50 60 80ns notes: 2943 tbl 13 1. port-to-port delay through ram cells from writing port to reading port, refer to "timing waveform of write with port-to-port read and busy ". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0, t wdd C t wp (actual), or t ddd C t dw (actual). 4. to ensure that the write cycle is inhibited on port "b" during contention on port "a". 5. to ensure that a write cycle is completed on port "b" after contention on port "a". 6. "x" in part numbers indicates power rating (s or l).
idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range 6.37 11 timing waveform of write with port-to-port read and busy busy busy busy busy (2,4,5) 2943 drw 13 t dw t aps addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for m/ s = v il (slave). 2. ce l = ce r = v il. 3. oe = v il for the reading port. 4. if m/ s = v il (slave), busy is an input. then for this example busy "a" = v ih and busy "b" input is shown above. 5. all timing is the same for left and right ports. port "a" may be either the left or right port. port "b" is the port opposite from port "a". timing waveform of write with busy notes: 1. t wh must be met for both busy input (slave) and output (master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 2943 drw 14 r/ w "a" busy "b" t wp t wb r/ w "b" t wh (2) (3) (1)
6.37 12 idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range waveform of busy arbitration controlled by ce ce ce ce ce timing (1) notes: 1. all timing is the same for left and right ports. port a may be either the left or right port. port b is the port opposite from port a. 2. if t aps is not satisfied, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted. note: 2942 tbl 14 1. "x" in part numbers indicates power rating (s or l). ac electrical characteristics over the operating temperature and supply voltage range (1) idt70v07x25 idt70v07x35 idt70v07x55 symbol parameter min. max. min. max. min. max. unit interrupt timing t as address set-up time 0 0 0 ns t wr write recovery time 0 0 0 ns t ins interrupt set time 25 30 40 ns t inr interrupt reset time 30 35 45 ns waveform of busy arbitration cycle controlled by address match timing (1) 2943 drw 15 addr "a" and "b" addresses match ce "a" ce "b" busy "b" t aps t bac t bdc (2) 2943 drw 16 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n"
idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range 6.37 13 waveform of interrupt timing (1) truth table iii interrupt flag (1) left port right port r/ w w w w w l ce ce ce ce ce l oe oe oe oe oe l a 14l -a 0l int int int int int l r/ w w w w w r ce ce ce ce ce r oe oe oe oe oe r a 14r -a 0r int int int int int r function l l x 7fff xxxxxl (2) set right int r flag x x x x x x l l 7fff h (3) reset right int r flag xx xxl (3) l l x 7ffe x set left int l flag x l l 7ffe h (2) xxxxx reset left int l flag notes: 2942 tbl 15 1. assumes busy l = busy r =v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. truth tables notes: 1. all timing is the same for left and right ports. port a may be either the left or right port. port b is the port opposite from port a. 2. see interrupt truth table. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. 2943 drw 17 addr "a" interrupt set address ce "a" r/ w "a" t as t wc t wr (3) (4) t ins (3) int "b" (2) 2943 drw 18 addr "b" interrupt clear address ce "b" oe "b" t as t rc (3) t inr (3) int "b" (2)
6.37 14 idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range functional description the idt70v07 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt70v07 has an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce high). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 7ffe (hex), where a write is defined as ce = r/ w = v il per the truth table. the left port clears the interrupt through access of address location 7ffe when ce r = oe r = v il , r/ w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 7fff (hex) and to clear the interrupt flag ( int r ), the right port must read the memory 7fff location 7fff. the message (8 bits) at 7ffe or 7fff is user-defined since it is an addressable sram location. if the interrupt function is not used, address locations 7ffe and 7fff are not used as mail boxes, but as part of the random access memory. refer to truth table for the interrupt operation. busy logic busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is busy. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applications. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an truth table iv address busyarbitration inputs outputs a 0l -a 14l ce ce ce ce ce l ce ce ce ce ce r a 0r -a 14r busy busy busy busy busy l (1) busy busy busy busy busy r (1) function xx no match h h normal hx match h h normal xh match h h normal ll match (2) (2) write inhibit (3) notes: 2943 tbl 16 1. pins busy l and busy r are both outputs when the part is configured as a master. both are inputs when configured as a slave. busy outputs on the idt7007 are push-pull, not open drain outputs. on slaves the busy input internally inhibits writes. 2. "l" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "h" if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. truth table v example of semaphore procurement sequence (1,2) functions d 0 - d 7 left d 0 - d 7 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free notes: 2943 tbl 17 1. this table denotes a sequence of events for only one of the eight semaphores on the idt70v07. 2. there are eight semaphore flags written to via i/o 0 and read from all i/o's (i/o 0 -i/o 7 ). these eight semaphores are addressed by a 0 - a 2 .
idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range 6.37 15 interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the m/ s pin. once in slave mode the busy pin operates solely as a write inhibit input pin. normal opera- tion can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt 70v07 ram in master mode, are push-pull type outputs and do not require pull up resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. width expansion with busy logic master/slave arrays when expanding an idt70v07 ram array in width while using busy logic, one master part is used to decide which side of the ram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the cmos static ram with an additional 8 address locations dedicated to binary semaphore flags. these flags allow either processor on the left or right side of the dual-port ram to claim a privilege over the other processor for functions defined by the system designers software. as an example, the sema- phore can be used by one processor to inhibit the other from accessing a portion of the dual-port ram or any other shared resource. the dual-port ram features a fast access time, and both ports are completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non-semaphore location. semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the dual-port ram. these devices have an automatic power-down feature controlled by ce , the dual-port ram enable, and sem , the semaphore enable. the ce and sem pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. this is the condition which is shown in truth table where ce and sem are both high. systems which can best use the idt70v07 contain mul- tiple processors or controllers and are typically very high- speed systems which are software controlled or software intensive. these systems can benefit from a performance increase offered by the idt70v07's hardware semaphores, which provide a lockout mechanism without requiring com- plex programming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. the idt70v07 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high-speed systems. how the semaphore flags work the semaphore logic is a set of eight latches which are independent of the dual-port ram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called token passing allocation. in this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then verifies its success in setting the latch by reading it. if it was successful, it proceeds to assume control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the same address range as the master, use the busy signal as a write inhibit signal. thus on the idt70v07 ram the busy pin is an output if the part is used as a master (m/ s pin = h), and the busy pin is an input if the part used as a slave (m/ s pin = l) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with the r/ w signal. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. semaphores the idt70v07 is an extremely fast dual-port 32k x 8 figure 3. busy and chip enable routing for both width and depth expansion with idt70v07 rams. 2943 drw 19 master dual port ram busy l busy r ce master dual port ram busy l busy r ce slave dual port ram busy l busy r ce slave dual port ram busy l busy r ce busy l busy r decoder
6.37 16 idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range left processor can then either repeatedly request that semaphores status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active low. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the idt70v07 in a separate memory space from the dual-port ram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, oe , and r/ w ) as they would be used in accessing a standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a0 C a2. when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see table iii). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communica- tions. (a thorough discussing on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. the read value is latched into one sides output register when that side's semaphore select ( sem ) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. because of this latch, a repeated read of a semaphore in a test loop must cause either signal ( sem or oe ) to go inactive or the output will never change. a sequence write/read must be used by the sema- phore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see table iii). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. d 2943 drw 20 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop l port r port semaphore read semaphore read figure 4. idt70v07 semaphore logic it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two semaphore request latches feed into a semaphore flag. whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. should the other sides semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first sides request latch. the second sides flag will now stay low until its semaphore request latch is written to a one. from this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simultaneous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming tech- nique, if semaphores are misused or misinterpreted, a soft- ware error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. using semaphoressome examples perhaps the simplest application of semaphores is their application as resource markers for the idt70v07s dual-port ram. say the 32k x 8 ram was to be divided into two 16k
idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range 6.37 17 x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. semaphore 0 could be used to indicate the side which would control the lower section of memory, and semaphore 1 could be defined as the indica- tor for the upper section of memory. to take a resource, in this example the lower 16k of dual-port ram, the processor on the left port could write and then read a zero in to semaphore 0. if this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 16k. meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into semaphore 0. at this point, the software could choose to try and gain control of the second 16k section by writing, then reading a zero into semaphore 1. if it succeeded in gaining control, it would lock out the left side. once the left side was finished with its task, it would write a one to semaphore 0 and may then try to gain access to semaphore 1. if semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into semaphore 1. if the right processor performs a similar task with semaphore 0, this protocol would allow the two processors to swap 16k blocks of dual-port ram with each other. the blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. all eight semaphores could be used to divide the dual-port ram or other shared resources into eight parts. semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. semaphores are a useful form of arbitration in systems like disk interfaces where the cpu must be locked out of a section of memory during a transfer and the i/o device cannot tolerate any wait states. with the use of semaphores, once the two devices has determined which memory area was off-limits to the cpu, both the cpu and the i/o devices could access their assigned portions of memory continuously without any wait states. semaphores are also useful in applications where no memory wait state is available on one or both sides. once a semaphore handshake has been performed, both proces- sors can access their assigned ram segments at full speed. another application is in the area of complex data struc- tures. in this case, block arbitration is very important. for this application one processor may be responsible for building and updating a data structure. the other processor then reads and interprets that data structure. if the interpreting processor reads an incomplete data structure, a major error condition may exist. therefore, some sort of arbitration must be used between the two different processors. the building processor arbitrates for the block, locks it and then is able to go in and update the data structure. when the update is completed, the data structure block is released. this allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
6.37 18 idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram commercial temperature range ordering information 2943 drw 21 a power 999 speed a package a process/ temperature range blank commercial (0 c to +70 c) pf g j 80-pin tqfp (pn80-1) 68-pin pga (g68-1) 68-pin plcc (j68-1) 25 35 55 s l standard power low power xxxxx device type 256k (32k x 8) 3.3v dual-port ram 70v07 idt speed in nanoseconds

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